High speed analog to digital converters (ADC) are typically used in electronics such as wireless receivers, cameras, modems, HDTV, and ultrasound systems. These electronics utilize sampling rates ranging between 40 MHz and 100 MHz for analog to digital conversion. At these frequencies, pipelined ADCs may provide low power consumption, low noise, and high speed. Pipeline ADCs are often used in applications where dynamic performance is of importance.
An active sample and hold amplifier is used in many configurations because it provides the ADC with a settled input voltage, allowing the subsequent circuit stages to capture the high frequency input signals. In order to achieve low power consumption and low noise while keeping performance high, some configurations remove the active sample and hold amplifier. The active sample and hold amplifier is not a necessity in ADCs and may also add noise and distortion to the analog input signal. In addition, an active sample and hold amplifier may consume large amounts of power and area on the die.
Aperture error in a typical ADC is the error caused by variation in the time at which the ADC transitions from sample mode to hold mode, usually resulting from noise on the clock or input signal. In a pipeline ADC architecture, sampling a continuous time signal, rather than a held signal in an active sample and hold device, may present additional aperture error. With reference to the pipeline ADC system 100 in FIG. 1A, this error results from a bandwidth mismatch of the sub-ADC 102 and the multiplying digital to analog converter (MDAC) 104. The aperture error in a pipeline ADC without active sample and hold can be demonstrated by the following equations.
Assuming a full-scale sine wave at the input:Vin=VREF×sin(2πfint)
The maximum slope of the signal is represented by:
                    ⅆ                  V          in                            ⅆ                                  ⁢        t              ⁢          |      Max        =            V      REF        ×    2    ⁢                  ⁢    π    ⁢                  ⁢          f      in      
If the time constant mismatch between the sub-ADC 102 and the MDAC 104 is Δτ=ε×τ, then the maximum aperture error may be represented by:Verror|Max=VREF×2πfin×ε×τ
For the 2.5 bit first stage, the error should be smaller than the correction range, that is Verror|Max<1/8VREF. In addition, the maximum input frequency fin of the input sampling networks of sub-ADC 102 and MDAC 104 should be less than or equal to
      0.1    τ    .The time constant error may then be represented by:
      ɛ    ⁢          |      Max        ⁢          <              1                  2          ⁢                                          ⁢          π          ×          0.1          ×          8                      =  0.2
Because the aperture error grows rapidly with respect to the input frequency, FIG. 1A utilizes a sampling switch 106. The sampling switch 106 is shared by both the sub-ADC 102 and the MDAC 104. Because the switch is shared, the aperture error can be reduced by matching the time constant of the sampling networks with the following equations:
                              2          ⁢                                          ⁢                      C            1                          +                  C                      p            ⁢                                                  ⁢            1                                                2          ⁢                                          ⁢                      C            2                          +                  C                      p            ⁢                                                  ⁢            2                                =                  1        /                  g          m                            R        sm              ;
            R      sm        =          1                        u          n                ⁢                  C          ox                ⁢                  W          L                ⁢                              (                                          V                gs                            -                              V                TH                                      )                    sm                      ;  and
      g    m    =            u      n        ⁢          C      ox        ⁢          W      L        ⁢          (                        V          gs                -                  V          TH                    )        ⁢          preamp      .      
In the above equations, gm is the transconductance of the preamplifier 108, RSm is the on-resistance of the MDAC switch 110, and Cp1 and Cp2 are the total parasitic capacitance at nodes T1 112 and T2 114. To optimize the time constant mismatch, the ratio of 1/gm to RSm should be set to 1. This approach, however, provides for increased power consumption by the preamplifiers 108.
As shown in FIG. 1B, the time window for TLATCH reduces the net amplification duration of MDAC 116. This scenario requires the operational transconductance amplifier of the MDAC 116 to consume twice the amount of power as compared to a traditional structure. Because the sampling duration is made shorter than the normal 50% duty cycle, the preamplifiers 108 must also be faster to complete their operations during TLATCH. The faster operation causes the preamplifiers to consume more power.
A typical approach to reducing the power consumption of the pipeline ADC circuit of FIG. 1A is shown in FIG. 2A. Compared with the system 100 in FIG. 1A, the pipeline ADC system 200 of FIG. 2A provides each flash comparator 202 and the MDAC 204 with their own input sampling switches 206a and 206b, respectively. Using separate sampling switches provides for no kickback from the latches 208 to the MDAC 204. Accordingly, each flash comparator 202 does not require a preamplifier and can only include a latch 208. Because there are no preamplifiers in the flash comparators 202, the sampling duration is shortened as compared to the typical 50% duty cycle, as shown in FIG. 2B. In contrast to FIG. 1A, however, there are no preamplifiers to consume power, so there is no power tradeoff at the MDAC 204.
Even though there is reduced power consumption in the system 200 of FIG. 2A as compared to the system 100 in FIG. 1A, the lack of preamplifiers in the flash comparators 202 creates a larger than normal input-inferred offset in each of the flash comparators 202. The large offset may occupy a significant portion of the digital correction range and leave only a small window for the aperture error correction.